Cell (microprocessor) - Wikipedia. Cell is a multi- coremicroprocessor microarchitecture that combines a general- purpose Power Architecturecore of modest performance with streamlined coprocessing elements[1] which greatly accelerate multimedia and vector processing applications, as well as many other forms of dedicated computation.[1]It was developed by Sony, Toshiba, and IBM, an alliance known as "STI". The architectural design and first implementation were carried out at the STI Design Center in Austin, Texas over a four- year period beginning March 2. Sony as approaching US$4. Cell is shorthand for Cell Broadband Engine Architecture, commonly abbreviated CBEA in full or Cell BE in part. The first major commercial application of Cell was in Sony's Play. Station 3game console. Mercury Computer Systems has a dual Cell server, a dual Cell blade configuration, a rugged computer, and a PCI Express accelerator board available in different stages of production. Toshiba had announced plans to incorporate Cell in high definition television sets, but seems to have abandoned the idea. Exotic features such as the XDR memory subsystem and coherent Element Interconnect Bus (EIB) interconnect[3] appear to position Cell for future applications in the supercomputing space to exploit the Cell processor's prowess in floating point kernels. ![]() The Cell architecture includes a memory coherence architecture that emphasizes power efficiency, prioritizes bandwidth over low latency, and favors peak computational throughput over simplicity of program code. For these reasons, Cell is widely regarded as a challenging environment for software development.[4] IBM provides a Linux- based development platform to help developers program for Cell chips.[5] The architecture will not be widely used unless it is adopted by the software development community. However, Cell's strengths may make it useful for scientific computing regardless of its mainstream success.[6]History[edit]. Cell BE as it appears in the PS3 on the motherboard. Peter Hofstee, one of the chief architects of the Cell microprocessor. In mid- 2. 00. 0, Sony Computer Entertainment, Toshiba Corporation, and IBM formed an alliance known as "STI" to design and manufacture the processor.[7]The STI Design Center opened in March 2. ![]() InformationWeek.com: News, analysis and research for business technology professionals, plus peer-to-peer knowledge sharing. Engage with our community. Search metadata Search full text of books Search TV captions Search archived web sites Advanced Search. July 06, 2017 09:45 PM - Office of Inadequate Security - Mike Eckel reports: A notorious Russian hacker whose exploits and later arrest gave glimpses into the. Arabic Office 2010 Professional Plus X86 Registers ReferenceThe Cell was designed over a period of four years, using enhanced versions of the design tools for the POWER4 processor. Over 4. 00 engineers from the three companies worked together in Austin, with critical support from eleven of IBM's design centers.[8] During this period, IBM filed many patents pertaining to the Cell architecture, manufacturing process, and software environment. An early patent version of the Broadband Engine was shown to be a chip package comprising four "Processing Elements", which was the patent's description for what is now known as the Power Processing Element (PPE). Each Processing Element contained 8 APUs, which are now referred to as SPEs on the current Broadband Engine chip. This chip package was widely regarded to run at a clock speed of 4 GHz and with 3. APUs providing 3. FLOPS each(FP8 quarter precision), the Broadband Engine was shown to have 1 tera. FLOPS of raw computing power. This design was fabricated using a 9. SOI process.[9]In March 2. Android Software Links: For the Android Mobile Telephone/Tablet Operating System by Google. Content by Respective Authors. IBM announced that the 6. Cell BE is in production at its plant (at the time, now Global. Foundries') in East Fishkill, New York.[9][1. Bandai Namco Entertainment used the cell processor for their 3. In February 2. 00. IBM announced that it will begin to fabricate Cell processors with the 4. In May 2. 00. 8, IBM introduced the high- performance double- precision floating- point version of the Cell processor, the Power. XCell 8i,[1. 2] at the 6. In May 2. 00. 8, an Opteron- and Power. XCell 8i- based supercomputer, the IBM Roadrunner system, became the world's first system to achieve one peta. FLOPS, and was the fastest computer in the world until third quarter 2. The world's three most energy efficient supercomputers, as represented by the Green. Power. XCell 8i. The 4. Cell processor was introduced in concert with Sony's Play. Station 3 Slim in August 2. By November 2. 00. IBM had discontinued the development of a Cell processor with 3. APUs[1. 4][1. 5] but was still developing other Cell products.[1. Commercialization[edit]On May 1. Sony Computer Entertainment confirmed some specifications of the Cell processor that would be shipping in the then- forthcoming Play. Station 3 console.[1. This Cell configuration has one PPE on the core, with eight physical SPEs in silicon.[1. In the Play. Station 3, one SPE is locked- out during the test process, a practice which helps to improve manufacturing yields, and another one is reserved for the OS, leaving 6 free SPEs to be used by games' code.[2. The target clock- frequency at introduction is 3. GHz.[1. 8] The introductory design is fabricated using a 9. SOI process, with initial volume production slated for IBM's facility in East Fishkill, New York.[9]The relationship between cores and threads is a common source of confusion. The PPE core is dual threaded and manifests in software as two independent threads of execution while each active SPE manifests as a single thread. In the Play. Station 3 configuration as described by Sony, the Cell processor provides nine independent threads of execution. On June 2. 8, 2. 00. IBM and Mercury Computer Systems announced a partnership agreement to build Cell- based computer systems for embedded applications such as medical imaging, industrial inspection, aerospace and defense, seismic processing, and telecommunications.[2. Mercury has since then released blades, conventional rack servers and PCI Express accelerator boards with Cell processors.[2. In the fall of 2. IBM released the QS2. Cell BE processors for tremendous performance in certain applications, reaching a peak of 4. FLOPS in FP8 quarter precision per module. The QS2. 2 based on the Power. XCell 8i processor is used for the IBM Roadrunner supercomputer. Mercury and IBM uses the fully utilized Cell processor with eight active SPEs. On April 8, 2. 00. Fixstars Corporation released a PCI Express accelerator board based on the Power. XCell 8i processor.[2. Sony's high performance media computing server ZEGO uses a 3. GHz Cell/B. E processor. Overview[edit]The Cell Broadband Engine, or Cell as it is more commonly known, is a microprocessor intended as a hybrid of conventional desktop processors (such as the Athlon 6. Core 2 families) and more specialized high- performance processors, such as the NVIDIA and ATI graphics- processors (GPUs). The longer name indicates its intended use, namely as a component in current and future online distribution systems; as such it may be utilized in high- definition displays and recording equipment, as well as HDTV systems. Additionally the processor may be suited to digital imaging systems (medical, scientific, etc.) and physical simulation (e. In a simple analysis, the Cell processor can be split into four components: external input and output structures, the main processor called the Power Processing Element (PPE) (a two- way simultaneous multithreaded. Power ISA v. 2. 0. Synergistic Processing Elements, or SPEs, and a specialized high- bandwidth circular data bus connecting the PPE, input/output elements and the SPEs, called the Element Interconnect Bus or EIB. To achieve the high performance needed for mathematically intensive tasks, such as decoding/encoding MPEG streams, generating or transforming three- dimensional data, or undertaking Fourier analysis of data, the Cell processor marries the SPEs and the PPE via EIB to give access, via fully cache coherent. DMA (direct memory access), to both main memory and to other external data storage. To make the best of EIB, and to overlap computation and data transfer, each of the nine processing elements (PPE and SPEs) is equipped with a DMA engine. Since the SPE's load/store instructions can only access its own local scratchpad memory, each SPE entirely depends on DMAs to transfer data to and from the main memory and other SPEs' local memories. A DMA operation can transfer either a single block area of size up to 1. KB, or a list of 2 to 2. One of the major design decisions in the architecture of Cell is the use of DMAs as a central means of intra- chip data transfer, with a view to enabling maximal asynchrony and concurrency in data processing inside a chip.[2.
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